MCQs on Pipelining in Computer Architecture for UGC-NET , GATE, SET and other examinations. Q1. In a 4-stage pipeline with stage delays of 60 ns, 50 ns, 90 ns, and 80 ns, and a latch delay of 10 ns, what is the pipeline cycle time? A. 90 ns B. 100 ns C. 110 ns D. 80 ns Answer: B. 100 ns Explanation: Maximum stage delay = 90 ns; Cycle time = 90 + 10 = 100 ns Q2. If non-pipelined execution takes 280 ns and pipelined execution takes 100 ns, what is the speed-up? A. 2.0 B. 2.5 C. 2.8 D. 3.0 Answer: C. 2.8 Explanation: Speed-up = 280 / 100 = 2.8 Q3. A pipeline has stage delays of 150 ns, 120 ns, 160 ns, and 140 ns. If the latch delay is 5 ns, what is the pipeline cycle time? A. 150 ns B. 155 ns C. 160 ns D. 165 ns Answer: D. 165 ns Explanation: Maximum stage delay = 160 ns; Cycle time = 160 + 5 = 165 ns Q4. A non-pipelined processor runs at 2.5 GHz and takes 4 cycles per instruction. A pipelined version runs at 2 GHz with 5 stages and no stalls. What is ...